rtoss - Diff between revs 74 and 79

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Rev 74 Rev 79
Line 2584... Line 2584...
2584     cirrus_linear_bitblt_writel, 2584     cirrus_linear_bitblt_writel,
2585 }; 2585 };
2586 2586
2587 static void map_linear_vram(CirrusVGAState *s) 2587 static void map_linear_vram(CirrusVGAState *s)
2588 { 2588 {
-   2589     if (!s->vga.vga_io_memory)
-   2590         return;
-   2591
2589     if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) { 2592     if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2590         s->vga.map_addr = s->vga.lfb_addr; 2593         s->vga.map_addr = s->vga.lfb_addr;
2591         s->vga.map_end = s->vga.lfb_end; 2594         s->vga.map_end = s->vga.lfb_end;
2592         cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset); 2595         cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2593     } 2596     }
Line 2617... Line 2620...
2617     vga_dirty_log_start(&s->vga); 2620     vga_dirty_log_start(&s->vga);
2618 } 2621 }
2619 2622
2620 static void unmap_linear_vram(CirrusVGAState *s) 2623 static void unmap_linear_vram(CirrusVGAState *s)
2621 { 2624 {
-   2625     if (!s->vga.vga_io_memory)
-   2626         return;
-   2627
2622     if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) 2628     if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
2623         s->vga.map_addr = s->vga.map_end = 0; 2629         s->vga.map_addr = s->vga.map_end = 0;
2624 2630
2625     cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000, 2631     cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2626                                  s->vga.vga_io_memory); 2632                                  s->vga.vga_io_memory);
Line 3060... Line 3066...
3060 3066
3061     s->cirrus_hidden_dac_lockindex = 5; 3067     s->cirrus_hidden_dac_lockindex = 5;
3062     s->cirrus_hidden_dac_data = 0; 3068     s->cirrus_hidden_dac_data = 0;
3063 } 3069 }
3064 3070
3065 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) -  
-   3071 static void cirrus_init_device(CirrusVGAState * s,
-   3072                                int device_id, int vram_size, int is_pci)
3066 { 3073 {
3067     int i; 3074     int i;
3068     static int inited; 3075     static int inited;
3069 3076
3070     if (!inited) { 3077     if (!inited) {
Line 3092... Line 3099...
3092             s->bustype = CIRRUS_BUSTYPE_PCI; 3099             s->bustype = CIRRUS_BUSTYPE_PCI;
3093         else 3100         else
3094             s->bustype = CIRRUS_BUSTYPE_ISA; 3101             s->bustype = CIRRUS_BUSTYPE_ISA;
3095     } 3102     }
3096 3103
-   3104     s->real_vram_size = vram_size;
-   3105
-   3106     /* XXX: s->vga.vram_size must be a power of two */
-   3107     s->cirrus_addr_mask = s->real_vram_size - 1;
-   3108     s->linear_mmio_mask = s->real_vram_size - 256;
-   3109
-   3110     s->vga.get_bpp = cirrus_get_bpp;
-   3111     s->vga.get_offsets = cirrus_get_offsets;
-   3112     s->vga.get_resolution = cirrus_get_resolution;
-   3113     s->vga.cursor_invalidate = cirrus_cursor_invalidate;
-   3114     s->vga.cursor_draw_line = cirrus_cursor_draw_line;
-   3115 }
-   3116
-   3117 static void cirrus_init_ioport(CirrusVGAState * s)
-   3118 {
3097     register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s); 3119     register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
3098 3120
3099     register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s); 3121     register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
3100     register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s); 3122     register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
3101     register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s); 3123     register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
Line 3124... Line 3146...
3124                                cirrus_linear_bitblt_write, s); 3146                                cirrus_linear_bitblt_write, s);
3125 3147
3126     /* I/O handler for memory-mapped I/O */ 3148     /* I/O handler for memory-mapped I/O */
3127     s->cirrus_mmio_io_addr = 3149     s->cirrus_mmio_io_addr =
3128         cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s); 3150         cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
-   3151 }
3129 3152
3130     s->real_vram_size = -  
-   3153 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
-   3154 {
-   3155     int vram_size =
3131         (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; 3156         (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3132 3157
3133     /* XXX: s->vga.vram_size must be a power of two */ -  
3134     s->cirrus_addr_mask = s->real_vram_size - 1; -  
3135     s->linear_mmio_mask = s->real_vram_size - 256; -  
3136 -  
3137     s->vga.get_bpp = cirrus_get_bpp; -  
3138     s->vga.get_offsets = cirrus_get_offsets; -  
3139     s->vga.get_resolution = cirrus_get_resolution; -  
3140     s->vga.cursor_invalidate = cirrus_cursor_invalidate; -  
3141     s->vga.cursor_draw_line = cirrus_cursor_draw_line; -  
3142 -  
-   3158     cirrus_init_device(s, device_id, vram_size, is_pci);
-   3159     cirrus_init_ioport(s);
3143     qemu_register_reset(cirrus_reset, s); 3160     qemu_register_reset(cirrus_reset, s);
3144     cirrus_reset(s); 3161     cirrus_reset(s);
3145 } 3162 }
3146 3163
3147 /*************************************** 3164 /***************************************
Line 3250... Line 3267...
3250 } 3267 }
3251 3268
3252 void pci_cirrus_vga_init(PCIBus *bus) 3269 void pci_cirrus_vga_init(PCIBus *bus)
3253 { 3270 {
3254     pci_create_simple(bus, -1, "Cirrus VGA"); 3271     pci_create_simple(bus, -1, "Cirrus VGA");
-   3272 }
-   3273
-   3274 /***************************************
-   3275  *
-   3276  *  NEC PC-9821
-   3277  *
-   3278  ***************************************/
-   3279
-   3280 uint32_t pc98_cirrus_vram_readb(void *opaque, target_phys_addr_t addr)
-   3281 {
-   3282     return cirrus_vga_mem_readb(opaque, addr & 0xffff);
-   3283 }
-   3284
-   3285 uint32_t pc98_cirrus_vram_readw(void *opaque, target_phys_addr_t addr)
-   3286 {
-   3287     return cirrus_vga_mem_readw(opaque, addr & 0xffff);
-   3288 }
-   3289
-   3290 uint32_t pc98_cirrus_vram_readl(void *opaque, target_phys_addr_t addr)
-   3291 {
-   3292     return cirrus_vga_mem_readl(opaque, addr & 0xffff);
-   3293 }
-   3294
-   3295 void pc98_cirrus_vram_writeb(void *opaque,
-   3296                              target_phys_addr_t addr, uint32_t value)
-   3297 {
-   3298     cirrus_vga_mem_writeb(opaque, addr & 0xffff, value);
-   3299 }
-   3300
-   3301 void pc98_cirrus_vram_writew(void *opaque,
-   3302                              target_phys_addr_t addr, uint32_t value)
-   3303 {
-   3304     cirrus_vga_mem_writew(opaque, addr & 0xffff, value);
-   3305 }
-   3306
-   3307 void pc98_cirrus_vram_writel(void *opaque,
-   3308                              target_phys_addr_t addr, uint32_t value)
-   3309 {
-   3310     cirrus_vga_mem_writel(opaque, addr & 0xffff, value);
-   3311 }
-   3312
-   3313 static uint32_t pc98_cirrus_vga_ioport_read(void *opaque,
-   3314                                             target_phys_addr_t addr)
-   3315 {
-   3316     addr = 0x300 | ((addr >> 8) & 0xf0) | (addr & 0x0f);
-   3317     return cirrus_vga_ioport_read(opaque, addr);
-   3318 }
-   3319
-   3320 static void pc98_cirrus_vga_ioport_write(void *opaque,
-   3321                                          target_phys_addr_t addr, uint32_t val)
-   3322 {
-   3323     addr = 0x300 | ((addr >> 8) & 0xf0) | (addr & 0x0f);
-   3324     cirrus_vga_ioport_write(opaque, addr, val);
-   3325 }
-   3326
-   3327 void *pc98_cirrus_vga_init(DisplayState *ds)
-   3328 {
-   3329     CirrusVGAState *s;
-   3330
-   3331     s = qemu_mallocz(sizeof(CirrusVGAState));
-   3332
-   3333     vga_common_init(&s->vga, PC98_CIRRUS_VRAM_SIZE);
-   3334     cirrus_init_device(s, CIRRUS_ID_CLGD5430, PC98_CIRRUS_VRAM_SIZE, 0);
-   3335
-   3336     register_ioport_write(0xca0, 16, 1, pc98_cirrus_vga_ioport_write, s);
-   3337     register_ioport_write(0xda4, 2, 1, pc98_cirrus_vga_ioport_write, s);
-   3338     register_ioport_write(0xdaa, 1, 1, pc98_cirrus_vga_ioport_write, s);
-   3339     register_ioport_read(0xca0, 16, 1, pc98_cirrus_vga_ioport_read, s);
-   3340     register_ioport_read(0xda4, 2, 1, pc98_cirrus_vga_ioport_read, s);
-   3341     register_ioport_read(0xdaa, 1, 1, pc98_cirrus_vga_ioport_read, s);
-   3342
-   3343     qemu_register_reset(cirrus_reset, s);
-   3344     cirrus_reset(s);
-   3345
-   3346     s->vga.ds = ds;
-   3347     vmstate_register(0, &vmstate_cirrus_vga, s);
-   3348
-   3349     return s;
-   3350 }
-   3351
-   3352 void pc98_cirrus_vga_invalidate_display_size(void *opaque)
-   3353 {
-   3354     CirrusVGAState *s = opaque;
-   3355
-   3356     s->vga.last_width = -1;
-   3357     s->vga.last_height = -1;
-   3358 }
-   3359
-   3360 void pc98_cirrus_vga_update_display(void *opaque)
-   3361 {
-   3362     CirrusVGAState *s = opaque;
-   3363
-   3364     s->vga.update(&s->vga);
-   3365 }
-   3366
-   3367 void pc98_cirrus_vga_invalidate_display(void *opaque)
-   3368 {
-   3369     CirrusVGAState *s = opaque;
-   3370
-   3371     s->vga.invalidate(&s->vga);
3255 } 3372 }
3256 3373
3257 static PCIDeviceInfo cirrus_vga_info = { 3374 static PCIDeviceInfo cirrus_vga_info = {
3258     .qdev.name    = "Cirrus VGA", 3375     .qdev.name    = "Cirrus VGA",
3259     .qdev.size    = sizeof(PCICirrusVGAState), 3376     .qdev.size    = sizeof(PCICirrusVGAState),